Frequently asked questions about our company & technology

CoolSem develops wafer-levelthermal solutions for semiconductor and photonic devices.

Our WaLTIS technology replaces the original device substrate with an engineered thermal and mechanical stack designed to improve heat removal close to the active device layer. At the same time, it can help manage coefficient of thermal expansion (CTE) mismatch between the device and the next level in the assembly.

By improving this part of the thermal path, WaLTIS can support higher performance, greater reliability, longer lifetime and more efficient system-level cooling.

As semiconductor and photonic devices become more powerful and compact, heat and thermo-mechanical stress increasingly limit performance, reliability and integration.

High thermal resistance close to the active device can lead to higher operating temperatures, reduced efficiency, performance derating and greater demands on package- and system-level cooling. Differences in thermal expansion between materials can also create mechanical stress, particularly in larger dies, brittle semiconductor materials and applications exposed to repeated thermal cycling.

CoolSem addresses these challenges by improving the thermal and mechanical architecture at device level, close to where the heat is generated: Cool at the Core.

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CoolSem addresses thermal performance at device level rather than relying only on improvements further downstream in the package or cooling system.

WaLTIS replaces the original device substrate after front-end fabrication with an engineered stack, designed specifically for the thermal, mechanical and electrical requirements of the final application.

This makes it possible to improve the first part of the thermal path, where significant bottlenecks can occur, while complementing existing package- and system-level cooling solutions.

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The WaLTIS stack is not intended to replace technologies such as thermal interface materials, heat spreaders, heat sinks, cold plates or liquid cooling. Instead, it improves the thermal path closer to the active device, before heat reaches those downstream cooling elements.

A stronger device-level thermal path can make package- and system-level cooling more effective and, depending on the application, may reduce the cooling effort, complexity or cost required elsewhere in the system.

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CoolSem focuses on applicationswhere thermal resistance, CTE mismatch or mechanical robustness createmeaningful limitations at device level.

Current priority areas include RF,photonics and optoelectronics, and selected power semiconductor applications.

Within these markets, CoolSem isparticularly relevant where higher power density, temperature-sensitiveperformance, demanding reliability requirements or challenging materialcombinations make conventional thermal approaches increasingly difficult.

CoolSem typically operates between front-end device fabrication and back-end packaging.

WaLTIS is integrated at wafer level after the active device has been fabricated and before final die packaging and module assembly.

This position allows CoolSem to improve the thermal and mechanical properties of the device without becoming part of the front-end device manufacturing process itself. The resulting benefits can then extend through the value chain to device manufacturers, module makers, system integrators and end users.

WaLTIS is CoolSem's Wafer-Level Thermal Interface Stack. It is an engineered wafer-level substrate consisting of multiple functional layers. WaLTIS is bonded to a thinned customer wafer and is designed to provide four main functions: improved thermal conduction from the device layer to the next level in the assembly; better CTE matching to support mechanical stability under thermal cycling; electrical isolation where required, including for high-voltage and RF applications; and mechanical support for the resulting bonded wafer stack, which is especially relevant for brittle materials such as InP. CoolSem's first generation is aimed at wafer sizes up to 200 mm, with larger wafer formats to be addressed in the second generation and through licensing models.

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WaLTIS is CoolSem's Wafer-Level Thermal Interface Stack: an engineered substrate that is integrated at wafer level after front-end device fabrication.

WaLTIS is bonded to a thinned device wafer and is designed to provide several functions within one integrated stack. Depending on the application, these can include improved thermal conduction, better CTE matching, electrical isolation and mechanical support.

By replacing the original device substrate with a stack optimized for the final application, WaLTIS improves the thermal and mechanical interface between the active device and the next level in the assembly.

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Temperature directly influences the performance and reliability of most semiconductor and photonic devices.

Depending on the application, excessive temperature can affect efficiency, output power, signal quality, wavelength stability, operating lifetime and long-term reliability. It can also force designers to derate devices or introduce more complex and costly cooling solutions.

Improving the thermal path therefore creates value not only by reducing temperature, but also by increasing the design freedom available at device, package and system level.

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Heat must travel from the active device through the substrate, package and ultimately into the system-level cooling solution.

If the first part of that thermal path has high thermal resistance, even an effective heatsink, cold plate or liquid cooling system cannot fully compensate for it.

By reducing thermal resistance closer to the heat source, CoolSem improves the path that heat must travel before it reaches downstream cooling. This can make the entire cooling architecture more effective.

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The original semiconductor substrate is primarily selected to enable growth, fabrication and processing of the device. It is therefore not necessarily optimized for thermal performance in the final product.

Depending on the material and device architecture, the substrate can represent a significant part of the thermal resistance between the active device region and the package or heatsink.

Differences in coefficient of thermal expansion between the device, substrate and package materials can also introduce mechanical stress during manufacturing and repeated thermal cycling.

The original substrate plays an essential role during device fabrication, but once the active device is complete it may no longer provide the best thermal and mechanical properties for the final application.

Removing the original substrate allows CoolSem to replace it with WaLTIS, an engineered stack designed specifically around the requirements of the finished device and application. This creates greater freedom to optimize thermal conductivity, thermal path length, CTE matching, electrical isolation and mechanical support.

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WaLTIS brings several functions together in one engineered wafer-level stack. Depending on the application, these can include a shorter and more conductive thermal path, improved CTE matching, electrical isolation and mechanical support for the thinned device wafer.

Combining these functions is important because an effective thermal solution must do more than conduct heat. It must also remain electrically suitable, mechanically stable and compatible with wafer processing, packaging and long-term operation.

The exact benefits depend on the device and application, but improved device-level thermal performance can create value in several ways.

Potential benefits include lower thermal resistance, lower operating temperature, improved performance stability, increased power density, greater reliability and longer lifetime. It can also reduce thermal design constraints and lower the cooling burden at package or system level.

In photonic applications, improved temperature control can additionally contribute to more stable optical and wavelength performance.

The most important benefit is therefore not always simply a cooler device. In some applications, greater value may be in higher performance, improved reliability or a simpler and more cost-effective system architecture.

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Yes. Thermal and thermo-mechanical limitations occur in both electronic and photonic devices, although the requirements and sources of value differ between applications.

CoolSem is developing WaLTIS as a platform technology that can be configured for both domains. Relevant applications include RF devices, photonics and optoelectronics, and selected power semiconductor applications.

WaLTIS is being developed as a platform technology for semiconductor and photonic devices where thermal performance, CTE mismatch or mechanical robustness are limiting factors. Relevant material platforms include GaN, GaAs, InP and SiC, among others.

The exact WaLTIS configuration and integration route depend on the device architecture, material system, wafer format and application requirements. This allows the technology to be adapted to different use cases rather than being limited to a single device type or semiconductor material.

WaLTIS is designed to integrate after front-end device fabrication. This means that, in many cases, the existing device design and upstream fabrication process can remain unchanged.

The WaLTIS integration step focuses on the substrate side of the device, replacing the original substrate with an engineered thermal and mechanical stack. The exact integration route depends on the device architecture and manufacturing flow, but the objective is to improve thermal performance without introducing unnecessary constraints upstream.

WaLTIS is introduced at wafer level after device fabrication and before final packaging and assembly. After integration, the resulting wafer or dies can continue into downstream processes such as die attach, substrate integration and module assembly. The aim is to improve the thermal and mechanical interface at device level while remaining compatible with established back-end manufacturing approaches. The exact process flow depends on the device, package architecture and application.

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CoolSem's first-generation WaLTIS technology is aimed at wafer sizes up to 200 mm. Larger wafer formats are planned as the technology and manufacturing platform develop further.

The appropriate wafer format and integration approach are assessed together with the specific device platform and application requirements.

Thermal conductivity is important, but it is only one part of the challenge.

A device-level thermal solution must also address the length of the thermal path, mechanical stability, coefficient of thermal expansion (CTE) mismatch, electrical requirements and compatibility with manufacturing and assembly.

WaLTIS is designed as an engineered stack rather than simply as a high-conductivity material. Depending on the application, it can combine improved thermal conduction with CTE matching, electrical isolation and mechanical support close to the active device layer.

CoolSem's WaLTIS technology is designed to significantly reduce the thermal resistance between the active device region and the next level in the thermal path. In reference configurations, CoolSem has demonstrated reductions in thermal resistance of up to 15× compared with the original device substrate.

The actual improvement in a specific product depends on factors such as device material, substrate thickness, die geometry, WaLTIS configuration and the surrounding package and cooling architecture. For this reason, thermal performance is evaluated for each application rather than assuming a fixed improvement factor.

The starting point is to understand where thermal or thermo-mechanical limitations occur in the device and whether improving the substrate-side thermal path can create meaningful value.

Relevant factors include the device material and architecture, wafer format, heat generation and power density, operating temperature, existing substrate, package configuration, CTE requirements, electrical isolation requirements and reliability targets.

Based on these inputs, CoolSem can assess whether WaLTIS is a suitable approach and what type of stack and integration route should be considered.

Engaging early can be valuable because thermal architecture, device design, packaging and reliability are closely connected. Early involvement provides more opportunity to evaluate the potential benefit of WaLTIS and to define an appropriate integration route.

However, WaLTIS is specifically designed to be introduced after device fabrication, which means that opportunities may also exist for established device platforms where the front-end process is already defined.

The best starting point is a discussion of the device, its thermal or mechanical limitations and the intended application.

Yes. A feasibility or development project can be used to evaluate how WaLTIS performs with a specific device platform and whether the technology can deliver sufficient thermal, mechanical and system-level value for the application.

The scope of such a project depends on the maturity of the device, wafer availability, integration requirements and the objectives of the evaluation. CoolSem works with customers and technology partners to define an appropriate development path for each case.

A few key details can help us quickly understand the application and determine the most relevant next steps. Useful information includes the device type and semiconductor material, wafer size, approximate die dimensions, power or heat load, size of hot spot(s), current substrate, package or module architecture and the main thermal or reliability challenge you are trying to solve.

Information about operating conditions, electrical isolation requirements, thermal cycling and the current stage of development can also be helpful.

You do not need to have all of this information available before contacting us. An initial discussion is often enough to determine whether WaLTIS could be relevant and what additional information would be useful.